The project may consist in a tutorial presentation, an implementation for tutuorial purposes or for the demonstration of parallel computing capabilities of some particular computing platform, etc. Please choose your project and contact me as soon as possible (Tudor.Jebelean@JKU.AT).

The projects are listed under the relevant bibliography. Other projects may also be accepted, please contact me if you have suggestions.

- T. Jebelean:
Systolic multiprecision arithmetic (PhD thesis), RISC report 94-37.
- Systolic algorithms for multiplication.
- Systolic algorithms for exact division.
- Systolic GCD using the generalization of the binary GCD algorithm.
- Hardware implementation of systolic multiplication.
- Hardware implementation of systolic exact division.
- Hardware implementation of systolic GCD.

- L. Ruff:
Generation and Verification of Systolic Algorithms (PhD Thesis).
- Design of a systolic polynomial multiplication using the space-time transformation methodology.
- Design of a unidirectional array for GCD computation using the functional-based approach.
- Design of a bidirectional array for online multiplication using the functional-based approach.

- B. Matasaru, T. Jebelean:
FPGA Implementation of an Extended Binary GCD Algorithm for Systolic Reduction of Rational Numbers Technical report no. 99-48.
- Hardware implementation of a systolic array for the reduction of rational fractions.

- T. Jebelean:
Using the Parallel Karatsuba Algorithm for Long Integer Multiplication and Division.
Technical report no. 97-08
- The Karatsuba algorithm for multiplication and its parallelization.
- The Karatsuba algorithm for division and its parallelization.

- T. Jebelean:
Auto-Configurable Array for GCD Computation.
Technical report no. 97-12
- Hardware implementation of an auto-cofigurable array for GCD computation.

- T. Jebelean:
Design of a Systolic Coprocessor for Rational Addition
Technical report no. 96-37
- Hardware implementation of a pipelining design for a sequence of arithmetic operations.